Nghĩa của từ one-address instruction bằng Tiếng Việt

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Đặt câu có từ "one-address instruction"

1. At least one predetermined bit of the instruction fetch address is used to select between the instruction sets.

2. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit.

3. The effective address of the access instruction is used without address translation to determine whether the level one cache for the processor core includes the data corresponding to the effective address.

4. The CPU sends a pointer address via the first address bus to the instruction mapping circuit.

5. Memory address where each instruction is located. For native applications, this is the actual memory address.

6. A further attribute may indicate that the fetch address is an even address in the instruction cache.

7. The address parts of BELL instructions may have three different meanings: address of a variable, address of an instruction, or constant.

8. If so, the instruction mapping circuit maps the pointer address to an address within the data cache.

9. Identifying the instruction to be fetched may include identifying an address stored in a program address pointer.

10. The data processing device has an instruction flow control unit that updates instruction addresses according the position dependent address steps.

11. The stored substitute address field may be adjusted after generating each instruction.

12. The programmer writes one mnemonic ( memory - aiding ) instruction for each machine - level instruction.

13. Device for assigning an instruction address coded to an electronic address recognition circuit, and for marking said circuit

14. An assembler language programmer writes one mnemonic instruction for each machine - level instruction.

15. Each byte offset identifies a memory address used by a machine code instruction.

16. If not, the pointer address is routed through the instruction mapping circuit unchanged.

17. In one embodiment, the microprocessor executes the x86 instruction set and the alternate instruction set is the ADSP 2171 instruction set.

18. An advanced load address table (ALAT) tracks status information for the advanced load instruction.

19. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data.

20. 26 Each byte offset identifies a memory address used by a machine code instruction.

21. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

22. In one embodiment, the microprocessor executes the x86 instruction set and the ADSP 2171 instruction set.

23. Virtually all instruction is in small groups or one-on-one.

24. Taking our hypothetical application with the 15000 byte virtual address space, assume that the application's first instruction accesses data stored at address 12374.

25. 16 One might question the wisdom of this instruction.

16 Một người có thể đặt nghi vấn về sự khôn ngoan của chỉ thị này.