Nghĩa của từ clock signal bằng Tiếng Đức

clock signal [klɔksignəl] Taktsignal

Đặt câu có từ "clock signal"

Dưới đây là những mẫu câu có chứa từ "clock signal", trong bộ từ điển Từ điển Anh - Đức. Chúng ta có thể tham khảo những mẫu câu này để đặt câu trong tình huống cần đặt câu với từ clock signal, hoặc tham khảo ngữ cảnh sử dụng từ clock signal trong bộ từ điển Từ điển Anh - Đức

1. A phase-lock loop generates an output clock signal from an input clock signal.

2. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay.

3. Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether.

4. Method and apparatus for counter-based clock signal adaptation

5. "Synchronous" sequential systems change state all at once, when a "clock" signal changes state.

6. For example, a clock signal is subject to the delays of any other electrical signal.

7. A display apparatus comprises a display panel; a resolution adjustor adjusting a resolution of a video signal and outputting the adjusted video signal and a pixel clock signal; a frequency adjustor adjusting a frequency of the pixel clock signal outputted from the resolution adjustor; and a controller controlling the frequency adjustor to adjust the frequency of the pixel clock signal in a blank range so as to correspond the number of the pixel clock signal from the resolution adjustor for a frame to the predetermined number.

8. An apparatus and method for recovering a clock signal from a Coded Marked Inversion (CMI) encoded signal.

9. The feedback amplifier applies the measured phase error as a DC offset to an AC differential clock signal.

10. The DVI data channel operates at a bit-rate that is 10 times the frequency of the clock signal.

11. Each of the second plates of the accumulation capacitors is connected to a second input terminal for receiving a clock signal.

12. Higher clock rates in increasingly complex CPUs make it more difficult to keep the clock signal in phase (synchronized) throughout the entire unit.

13. A bandpass sampling receiver is proposed for receiving RF signals, comprising: the first ADC, for converting the RF signal into the first path of digital signal under the control of the first sampling clock signal; the second ADC, for converting the RF signal into the second path of digital signal under the control of the second sampling clock signal; a signal separating unit, for separating the in-phase signal and the quadrature signal in the first path of digital signal and the second path of digital signal; wherein the frequency of said first sampling clock signal and said second sampling clock signal is 1/N of that of said RF signal, and N is a natural number.

14. The sampling rate of the A/D converters (103a-103b) is controlled by a sampling clock signal (104) generated by a timing recovery circuit (107).

15. 29 Never gate your clock signal with combinational logic. Glitches may occur on any gated clock signals, which results in false triggering of flip-flops.

16. Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, limited largely by the speed of the switching devices they were built with.

17. According to said method, the clock signal (CLt, CLc) to be corrected is applied to the respective gate of the MOS transistor pair (T1, T2), and a differential analog pulse duty correction signal (DCt, DCc) is produced by respective integration of the true and complementary clock signal (ACLt, ACLc) emitted by every MOS transistor (T1, T2) of the differential amplifier (1) on its source/drain connection.

Dabei wird das zu korrigierende Taktsignal (CLt, CLc) an einen jeweiligen Gateanschluss des MOS-Transistorpaars (Tl, T2) angelegt, ein differentielles analoges Tastverhältniskorrektursignals (DCt, DCc) durch jeweilige Integration des von jedem MOS-Transistor (Tl, T2) des Differenzverstärkers (1) an seinem Source/Drainanschluss abgegebenen wahren und komplementären Taktsignals (ACLt, ACLc) erzeugt und das so erzeugte differentielle Tastverhältniskorrektursignals (DCt, DCc) jeweils an die elektrisch voneinander getrennten Substratanschlüsse (Sl, S2) des MOS- Transistorpaars (Tl, T2) angelegt, so dass jeweils die Substratspannungen und damit die Einsatzspannungen der MOS- Transistoren (Tl, T2) des Transistorpaars gegensinnig beeinflusst werden.

18. A subset of the plurality of amplifier cells receiving each phase clock signal are enabled, based on the magnitude of the associated vector describing the signal in affine transform space.

19. According to Wikipedia, in digital logic and computing, a Counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal

20. Cycle-to-cycle jitter of ±3ns applied to the input clock signal while data inputs are switching (see figures 15 and 16).Ajitter event of 3ns, represents worse case jump in the clock edge from most graphics VGA chips currently available

21. According to Wikipedia, in digital logic and computing, a Counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. Counters are used in digital electronics for counting purpose, they can count specific event happening in the circuit.